Dynamic random access memories (DRAMs) are indispensable to a variety of computing devices. In general, a DRAM operates at fixed power and fixed frequency. When a computing device operates in a power saving mode, although an external voltage provided for the DRAM is decreased, the consuming power and the operation frequency are not dramatically decreased due to the circuit structure inside the DRAM. When the computing device is in a high power efficiency mode, although the external voltage provided for the DRAM is increased, the consuming power and the operation frequency are not dramatically increased due to the aforementioned reasons. Thus, that the power and the operation frequency could be adjusted for the DRAMs based on requirements is needed.